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关 键 词：stm32固件库使用手册,百度网盘
行 业：电子 电子产品设计
发布时间：2023-01-05
ATtiny88 Automotive 8-bit AVR Microcontroller with 8K Bytes In-System Programmable Flash DATASHEET Features High performance, low power AVR 8-Bit microcontroller Advanced RISC architecture 123 powerful instructions most single clock cycle e...
Peripheral Features– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode– One 16-bit Timer/Counter with Prescaler, and Compare and Capture Modes– 6- or 8-channel 10-bit ADC– Master/Slave SPI Serial Interface– Byte-oriented 2-wire Serial Interface (Philips I2C Compatible)– Programmable Watchdog Timer with Separate On-Chip Oscillator– On-Chip Analog Comparator– Interrupt and Wake-up on Pin Change•
ThePD[7:4] output buffers have symmetrical drive characteristics with both sink and source capabil-ities, while the PD[3:0] output buffers have high sink capabilities. As inputs, Port D pins that areexternally pulled low will source current if the pull-up resistors are activated. The Port D pins aretri-stated when a reset condition becomes active, even if the clock is not running.The various special features of Port D are elaborated in “Alternate Functions of Port D” on page75.
minimum pulse length is given in Table 22-3 on page 209. Shorter pulses are not guaranteed togenerate a reset.The various special features of Port C are elaborated in “Alternate Functions of Port C” on page72.1.1.8Port D (PD7:0)Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit).
Special Microcontroller Features– debugWIRE On-Chip Debug System– In-System Programmable via SPI Port– Power-On Reset and Programmable Brown-Out Detection– Internal Calibrated Oscillator– External and Internal Interrupt Sources– Three Sleep Modes: Idle, ADC Noise Reduction and Power-Down– On-Chip Temperature Sensor•
The ATtiny48/88 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISCarchitecture. By executing powerful instructions in a single clock cycle, the ATtiny48/88 achievesthroughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con-sumption versus processing speed.
