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关 键 词：华为手机版本号命名规则
行 业：电子 电子产品设计
发布时间：2022-12-25
ATtiny88 Automotive 8-bit AVR Microcontroller with 8K Bytes In-System Programmable Flash DATASHEET Features High performance, low power AVR 8-Bit microcontroller Advanced RISC architecture 123 powerful instructions most single clock cycle e...
The Port B pins are tri-stated when a reset condition becomes active, even if the clockis not running.Depending on the clock selection fuse settings, PB6 can be used as input to the internal clockoperating circuit.The various special features of Port B are elaborated in “Alternate Functions of Port B” on page69.1.1.6Port C (PC7, PC5:0)Port C is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit).
ThePD[7:4] output buffers have symmetrical drive characteristics with both sink and source capabil-ities, while the PD[3:0] output buffers have high sink capabilities. As inputs, Port D pins that areexternally pulled low will source current if the pull-up resistors are activated. The Port D pins aretri-stated when a reset condition becomes active, even if the clock is not running.The various special features of Port D are elaborated in “Alternate Functions of Port D” on page75.
PC6 is used as an I/O pin. Note that the electrical char-acteristics of PC6 differ from those of the other pins of Port C.If the RSTDISBL Fuse is unprogrammed, PC6 is used as a reset input. A low level on this pin forlonger than the minimum pulse width will generate a reset, even if the clock is not running. The
minimum pulse length is given in Table 22-3 on page 209. Shorter pulses are not guaranteed togenerate a reset.The various special features of Port C are elaborated in “Alternate Functions of Port C” on page72.1.1.8Port D (PD7:0)Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit).
The ATtiny48/88 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISCarchitecture. By executing powerful instructions in a single clock cycle, the ATtiny48/88 achievesthroughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con-sumption versus processing speed.
