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关 键 词:AT32AP7002-CTUT
行 业:电子 电子有源器件 专用集成电路
发布时间:2022-01-15
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Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index Name Bits Description
VDS_MTHD 6 Input data double sample Method.
0: Using average.
1: Using advance GT filter.
IVDS 5 Input VSYNC Delay Select.
0: Delay 1/4 input HSYNC (recommended).
1: No delay.
HES 4 Input HSYNC reference Edge Select.
0: From HSYNC leading edge, default value.
1: From HSYNC tailing edge.
VES 3 Input VSYNC reference Edge Select.
0: From VSYNC leading edge, default value.
1: From VSYNC tailing edge.
ESLS 2 Early Sample Line Select.
0: 8 lines.
1: 16 lines.
VWRP 1 Input image Vertical Wrap.
0: Disable.
1: Enable.
HWRP 0 Input image Horizontal Wrap.
0: Disable.
1: Enable.
04h ISCTRL 7:0 Default : 0x10 Access : R/W
DDE 7 Direct DE mode for CCIR input.
0: Disable direct DE.
1: Enable direct DE.
DEGR[2:0] 6:4 DE or HSYNC post Glitch removal Range.
HSFL 3 Input HSYNC Filter.
0: Filter off.
1: Filter on.
ISSM 2 Input Sync Sample Mode.
0: Normal.
1: Glitch-removal.
MVD_SEL 1:0 MVD mode Select
0: CVBS.
1: S-Video.
2: YCbCr.
3: RGB.
05h SPRVST_L 7:0 Default : 0x10 Access : R/W, DB
Sigmastar Confidential for
芯智国际有限公司
Internal Use Only
Security Level: Confidential A
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index Name Bits Description
SPRVST[7:0] 7:0 Image vertical sample start point, count by input HSYNC (lower 8
bits).
06h SPRVST_H 7:0 Default : 0x00 Access : R/W, DB
- 7:3 Reserved.
SPRVST[10:8] 2:0 Image vertical sample start point, count by input HSYNC (higher 3
bits).
07h SPRHST_L 7:0 Default : 0x01 Access : R/W, DB
SPRHST[7:0] 7:0 Image horizontal sample start point, count by input dot clock
(lower 8 bits).
08h SPRHST_H 7:0 Default : 0x00 Access : R/W, DB
- 7:4 Reserved.
SPRHST[11:8] 3:0 Image horizontal sample start point, count by input dot clock
(higher 4 bits).
09h SPRVDC_L 7:0 Default : 0x10 Access : R/W, DB
SPRVDC[7:0] 7:0 Image vertical resolution (vertical display enable area count by
line; lower 8 bits).
0Ah SPRVDC_H 7:0 Default: 0x00 Access : R/W
- 7:3 Reserved.
SPRVDC[10:8] 2:0 Image vertical resolution (vertical display enable area count by
line; higher 3 bits).
0Bh SPRHDC_L 7:0 Default : 0x10 Access : R/W
SPRHDC[7:0] 7:0 Image horizontal resolution (horizontal display enable area count
by pixel; lower 8 bits).
0Ch SPRHDC_L 7:0 Default : 0x00 Access : R/W
- 7:3 Reserved.
SPRHDC[11:8] 3:0 Image horizontal resolution (horizontal display enable area count
by pixel; higher 4 bits).
0Dh LYL 7:0 Default : 0x00 Access : R/W
- 7:4 Reserved.
LYL[3:0] 3:0 Lock Y Line.
0Eh INTLX 7:0 Default : 0x00 Access : -
ITU_EXT_FIELD 7 Using External FIELD for ITU interface.
Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index Name Bits Description
TRGC 1 Trigger Condition.
0: Active low for level trigger/tailing edge trigger.
1: Active high for level trigger/leading edge trigger.
INT_TRIG 0 Interrupt Trigger.
0: Generate an edge trigger interrupt.
1: Generate a level trigger interrupt.
17h INTPULSE 7:0 Default : 0x0F Access : R/W
INTPULSE[7:0] 7:0 Interrupt Pulse width by reference clock.
18h INTSTA 7:0 Default : 0x00 Access : R/W
INTSTA[7:0] 7:0 Interrupt Status byte A.
Bit 7: MVD input NOT “no signal”.
Bit 6: MVD “HSYNC lock”.
Bit 5: MVD NOT “no color”.
Bit 4: MVD degree error.
Bit 3: MVD input “no signal”.
Bit 2: MVD NOT “HSYNC lock”.
Bit 1: MVD “no color”.
Bit 0: MVD HSYNC change.
19h INTENA 7:0 Default : 0x00 Access : R/W
INTENA[7:0] 7:0 Interrupt Enable control byte A.
0: Disable interrupt.
1: Enable interrupt.
1Ah INTSTB 7:0 Default : 0x00 Access : R/W
INTSTB[7:0] 7:0 Interrupt Status byte B.
Bit 7: MCU D2B interrupt 2.
Bit 6: MCU D2B interrupt 1.
Bit 5: MCU D2B interrupt 0.
Bit 4: MVD CC interrupt.
Bit 3: MVD SECAM detect.
Bit 2: MVD PAL switch error.
Bit 1: MVD “ADC7_0ACT”.
Bit 0: MVD NOT “ADC7_0ACT”.
1Bh INTENB 7:0 Default : 0x00 Access : R/C
INTENB[7:0] 7:0 Interrupt Enable control byte B.
0: Disable interrupt.
1: Enable interrupt.
1Ch INTSTC 7:0 Default : 0x00 Access : R/W
Sigmastar Confidential for
芯智国际有限公司
Internal Use Only
Security Level: Confidential A
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index Name Bits Description
INTSTC[7:0] 7:0 Interrupt Status byte C.
Bit 7: Output VSYNC interrupt.
Bit 6: Input VSYNC interrupt.
Bit 5: ATG ready interrupt.
Bit 4: ATP ready interrupt.
Bit 3: ATS ready interrupt.
Bit 2: MVD probe ready interrupt.
Bit 1: MCU D2B interrupt 4.
Bit 0: MCU D2B interrupt 3.
1Dh INTENC 7:0 Default : 0x00 Access : R/C
INTENC[7:0] 7:0 Interrupt Enable control byte C.
0: Disable interrupt.
1: Enable interrupt.
1Eh INTSTD 7:0 Default : 0x00 Access : R/W
INTSTD[7:0] 7:0 Interrupt Status byte D.
Bit 7: WDT interrupt.
Bit 6: Keypad wake-up interrupt.
Bit 5: Jitter interrupt.
Bit 4: Horizontal total change interrupt.
Bit 3: Vertical total change interrupt.
Bit 2: Horizontal lost count interrupt.
Bit 1: Vertical lost count interrupt.
Bit 0: Standard change interrupt.
1Fh INTEND 7:0 Default : 0x00 Access : R/C
INTEND[7:0] 7:0 Interrupt Enable control byte D.
0: Disable interrupt.
1: Enable interrupt.
20h ~
21h
- 7:0 Default : - Access : -
- 7:0 Reserved.
22h MPL_M 7:0 Default : 0x6F Access : R/W
MP_ICTRL[2:0] 7:5 Charge pump current set.
MPL_M[4:0] 4:0 MPLL divider ratio setting.
23h OPL_CTL0 7:0 Default : 0x40 Access : R/W
- 7:6 Reserved.
_EN 6 Output PLL spread spectrum.
0: Disable.
1: Enable
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