深圳市伟格兴电子科技有限公司是一家大型集成电路代理,分销商,公司在深圳.作为的集成电路分销商，我公司拥有丰富经验的IC销售人员，为客户提供全面的服务支持。我公司主要从事美国ADI、MAXIM，TI，ON，ST，FAIRCHILD，ADI，NXP等世界的IC和功率模块 GTR、IGBT、IPM、PIM可控硅 整流桥 二极管等，涵盖通信、半导体、仪器仪表、航天航空、计算机及周边产品、消费类电子等广泛领域。公司多，价格合理。经过我公司全体人员的共同努力， 深圳市伟格兴电子科技有限公司现已成为国有大、中型企业，企业，中小型分销商的可靠合作伙伴，业务遍及中国大陆及海外市场。 我公司在国外拥有直接的货源和存货，与国际上享有良好声誉的大量供应商建立了良好的长期合作关系。定货渠道好，周期短，以‘交货快捷、质量保证、价格合理’为服务的宗旨，保证所提供货品均为原包装。 我公司一贯坚持：“品质、服务至上”的发展宗旨以向用户提供系统 免费技术解决方案和满意的服务为己任。我们希望结交更多的合作伙伴，以合理的价格、的服务，与大家共同开创广阔的未来！同时也希望与业界同行进行广泛的交流与合作，共同为电子业繁荣发展作出自己的贡献！
东芝提供专为各种车载通信应用而特别设计的RF IC。 这些IC提供有关交通拥堵、事故、公路路口状况等的实时语音导航，并允许注册车辆通过收费站时无需停车进行缴费，从而改善了驾驶体验。
电子道路收费（ETC）系统
短程通信（DSRC）
多车道自由流（MLFF）： 允许多条相邻车道上的驾驶员能够同时与RSU进行通信，无需减速实施缴费，无需设置收费关卡。
Digital Panel Output Interface
Pin Name Pin Type Function Pin
CLKO Output Display Clock Output 53
DEO/TCON[10] Output Display Enable Output 54
VSYNCO/TCON[9] Output Vertical Sync Output / TCON Output[9] 55
HSYNCO/TCON[8] Output Horizontal Sync Output / TCON Output[8] 56
ROUT[7]/TCON[6] Output Red channel Output [7] / TCON Output[6] 67
ROUT[6]/TCON[7] Output Red channel Output [6] / TCON Output[7] 66
ROUT[5] Output Red channel Output [5] 65
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芯智国际有限公司
Internal Use Only
SSD102
Smart HD Display Controller
Preliminary Data Sheet Version 0.1
Security Level: Confidential A - 8 - 2/27/2018
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
Pin Name Pin Type Function Pin
ROUT[4] Output Red channel Output [4] 64
ROUT[3] Output Red channel Output [3] 63
ROUT[2] Output Red channel Output [2] 62
ROUT[1] Output Red channel Output [1] 61
ROUT[0] Output Red channel Output [0] 60
GOUT[7]/TCON[4] Output Green channel Output [7] / TCON Output[4] 75
GOUT[6]/TCON[5] Output Green channel Output [6] / TCON Output[5] 74
GOUT[5:4] Output Green channel Output [5:4] 73, 72
GOUT[3] Output Green channel Output [3] 71
GOUT[2] Output Green channel Output [2] 70
GOUT[1] Output Green channel Output [1] 69
GOUT[0] Output Green channel Output [0] 68
BOUT[7]/TCON[2] Output Blue channel Output [7] / TCON Output[2] 90
BOUT[6]/TCON[3] Output Blue channel Output [6] / TCON Output[3] 89
BOUT[5:0] Output Blue channel Output [5:0] 88-83
TCON[0] Output TCON Output[1] 92
Digital Video Input Interface
Pin Name Pin Type Function Pin
CLKIN Input w/5V-tolerant Sample Clock ITU656 Video Input 26
VD[7:0] Input w/5V-tolerant ITU656 Video Data bus 34-27
GPIO Interface
Pin Name Pin Type Function Pin
GPIOA I/O w/ 5V-tolerant General Purpose Input Output; 4mA driving strength 45
GPIOD I/O w/ 5V-tolerant General Purpose Input Output; 4mA driving strength 93
GPIOE I/O w/ 5V-tolerant General Purpose Input Output; 4mA driving strength 94
I2C Master Interface
Pin Name Pin Type Function Pin
I2CMD/TXD_SDA I/O w/ 5V-tolerant,
w/ pull-up resistor
Serial Bus Data 22
I2CMC/RXD_SCL I/O w/ 5V-tolerant
w/ pull-up resistor
Serial Bus Clock 21
Sigmastar Confidential for
芯智国际有限公司
Internal Use Only
SSD102
Smart HD Display Controller
Preliminary Data Sheet Version 0.1
Security Level: Confidential A - 9 - 2/27/2018
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
Misc. Interface
Pin Name Pin Type Function Pin
RESET Schmitt Trigger Input
w/ 5V-tolerant
Hardware Reset; active high 52
XTAL_IN Analog Input Crystal Oscillator Input 99
XTAL_OUT Analog Output Crystal Oscillator Output 98
Power Pins
Pin Name Pin Type Function Pin
AVDD_ANA 3.3V Power Analog ADC Power 1
AVDD_MPLL 3.3V Power MPLL Power 100
VDDC 1.2V Power Digital Core Power 35, 57
VDDP 3.3V Power Digital Input/Output Power 23, 58, 82
AGND Ground Analog Ground 9, 97
GND Ground Ground 20, 36, 37,
49, 59, 78,
91
No Connect
Pin Name Pin Type Function Pin
NC
No Connects 76, 77,
79-81
Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index Name Bits Description
SD_MD 5 Output PLL spread spectrum Mode.
0: Normal.
1: Reverse for mode 1.
- 4:0 Reserved.
24h - 7:0 Default : - Access : -
- 7:0 Reserved.
25h OPL_SET0 7:0 Default : 0x44 Access : R/W, DB
OPL_SET[7:0] 7:0 Output PLL Set.
26h OPL_SET1 7:0 Default : 0x55 Access : R/W, DB
OPL_SET[15:8] 7:0 See description for OPL_SET [7:0].
27h OPL_SET2 7:0 Default : 0x24 Access : R/W, DB
OPL_SET [23:16] 7:0 See description for OPL_SET [7:0].
28h OPL_STEP0 7:0 Default : 0x20 Access : R/W, DB
OPL_STEP[7:0] 7:0 Output PLL spread spectrum Step.
29h OPL_STEP1 7:0 Default : 0x00 Access : R/W, DB
- 7 Reserved.
- 6 Reserved.
- 5 Reserved.
- 4:3 Reserved.
OPL_STEP[10:8] 2:0 See description for OPL_STEP[7:0].
2Ah OPL_SPAN 7:0 Default : 0x00 Access : R/W, DB
OPL_SPAN[7:0] 7:0 Output PLL spread spectrum Span.
2Bh OPL_SPAN 7:0 Default : 0x00 Access : R/W, DB
READ_FRAME 7 0: OPL_SET stores line-based value.
1: OPL_SET stores frame-based value.
OPL_SPAN[14:8] 6:0 See description for OPL_SPAN[7:0].
2Ch ~
2Fh
- 7:0 Default : - Access : -
- 7:0 Reserved.
30h HSR_L 7:0 Default : 0x00 Access : R/W
HSR [7:0] 7:0 Horizontal Scaling ratio (20 bits fraction) for scaling down 1/2^20
to (2^20-1)/2^20 (lower 8 bits).
31h HSR_M 7:0 Default : 0x00 Access : R/W
HSR[15:8] 7:0 Horizontal Scaling ratio (20 bits fraction) for scaling down 1/2^20
to (2^20-1)/2^20 (middle 8 bits).
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Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index Name Bits Description
32h HSR_H 7:0 Default : 0x00 Access : R/W
HS_EN 7 Horizontal Scaling Enable.
0: Disable.
1: Enable.
CBILINEAR_EN 6 Complemental Bi-Linear Enable.
FORCEBICOLOR 5 0: Chrominance using same setting as Luminance defined by
CBILINEAR.
1: Chrominance always using bi-linear algorithm.
- 4 Reserved.
HSR[19:16] 3:0 Horizontal Scaling Ratio (20 bits fraction) for scaling down 1/2^20
to (2^20-1)/2^20 (higher 8 bits).
33h VSR_L 7:0 Default : 0x00 Access : R/W
VSR[7:0] 7:0 Vertical Scaling ratio (2 bits integer, 20 bits fraction) for scaling
down to 1/2.9999 (lower 8 bits).
xx.xxxxxxxxxxxxxxxxxxxx
34h VSR_M 7:0 Default : 0x00 Access : R/W
VSR[15:8] 7:0 Vertical Scaling ratio (2 bits integer, 20 bits fraction) for scaling
down to 1/2.9999 (middle 8 bits).
xx.xxxxxxxxxxxxxxxxxxxx
35h VSR_H 7:0 Default : 0x00 Access : R/W
VS_EN 7 Vertical Scaling Enable.
0: Disable.
1: Enable.
VSM_SEL 6 Vertical Scaling Method Select.
0: Original.
1: New.
VSR[21:16] 5:0 Vertical Scaling ratio (2 bits integer, 20 bits fraction) for scaling
down to 1/2.9999 (higher 8 bits).
xx.xxxxxxxxxxxxxxxxxxxx
36h VDSUSG 7:0 Default: 0x00 Access : R/W
LBF_INCLK 7 Line-Buffer using Input Clock.
LBF_OUTCLK 6 Line-Buffer using Output Clock.
LBF_LIVE 5 Line-Buffer always Live.
OUTCLK_DIV3 4 Output Clock is 1/3 frequency of OPLL output.
EN_OFST 3 Enable Offset for even/odd scaling.
OFST_INV 2 Offset Inverting for even/odd scaling.
Security Level: Confidential A - 12 - 2/27/2018
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
ORDERING GUIDE
Part Number Temperature Range Package Description Package Option
SSD102 -40°C to +85°C LQFP 100-pin
MARKING INFORMATION
SSD102
DISCLAIMER
SIGMASTAR TECHNOLOGY RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE
TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. NO
RESPONSIBILITY IS ASSUMED BY SIGMASTAR TECHNOLOGY ARISING OUT OF THE APPLICATION
OR USER OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY
LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
Electrostatic charges accumulate on both test equipment and human body and can discharge without
detection. SSD102 comes with ESD protection circuitry; however, the device may be permanently
damaged when subjected to high energy discharges. The device should be handled with proper ESD
precautions to prevent malfunction and performance degradation.
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Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
REGISTER DESCRIPTION
General Control Register
General Control Register
Index Name Bits Description
00h
REGBK 7:0 Default : 0x00 Access : R/W
XTAL_OK (RO) 7 Crystal ready.
MCU_SEL (RO) 6 0: Embedded MCU.
1: External serial bus interface.
- 5:4 Reserved.
AINC 3 Serial bus address auto Increase.
0: Enable.
1: Disable.
- 2 Reserved.
REGBK[1:0] 1:0 Register Bank Select.
00: Register of scaler.
01: Register of ADC/ACE/MCU.
10: Register of Video Decoder Front End (VFE).
11: Register of Video Decoder 2D Comb Filter (VCF).
REGBK[2:0] 2:0 Register Bank Select.
000: Register of scaler.
001: Register of ADC/ACE/MCU.
010: Register of Video Decoder Front End (VFE).
011: Register of Video Decoder 2D Comb Filter (VCF)
01h ~
FFh
- 7:0 Default : - Access : -
- 7:0 Reserved.
Scaler Register (Bank = 00, Registers 01h ~ 9Fh)
Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index Name Bits Description
01h
DBFC 7:0 Default : 0x80 Access : R/W
- 7:3 Reserved.
DBL[1:0] 2:1 Double Buffer Load.
00: Keep old register value.
01: Load new data (auto reset to 00 when load finish).
10: Automatically load data at VSYNC blanking.
11: Reserved.
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Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index Name Bits Description
DB_EN 0 Double Buffer Enable.
0: Disable.
1: Enable.
02h ISELECT 7:0 Default : 0x00 Access : R/W
NIS 7 No Input Source.
0: Input source active.
1: Input source inactive, output is free-run.
STYPE[1:0] 6:5 Input Sync Type.
00: Auto detected.
01: Input is separated HSYNC and VSYNC.
10: Input is Composite sync.
11: Input is sync-on-green (SOG).
COMP 4 CSYNC/SOG select (only useful when STYPE = 00).
0: CSYNC.
1: SOG.
ICS 3 Input Color Space.
0: RGB.
1: YCbCr.
IHSU 2 Input Sync Usage.
When EXTVD=0:
0: Use HSYNC to perform mode detection, HSOUT from ADC to
sample pixel.
1: Use HSYNC only.
When EXTVD=1:
0: Normal.
1: Output black at blanking.
BYPASSMD 1 By-Pass Mode for interlace-input-interlace-output.
EXTVD 0 0: Select analog input (CVBS/S-Video/RGB/YCbCr).
1: Select digital input (CCIR656).
03h IPCTRL2 7:0 Default : 0x18 Access : R/W
VDS_EN 7 Input data double sample
In CCIR input mode,
0: for horizontal output resolution less than 720 pixels.
1: for horizontal output resolution more than 720 pixels.
In analog input mode,
0: half sample of input data.
1: original sample of input data.
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