价格：面议
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产品规格：工业级
产品数量：1000000 个
包装说明：原包装
关 键 词：PIC24FJ64GA006
行 业：
发布时间：2014-02-14
High-Performance CPU: • Modified Harvard Architecture • Up to 16 MIPS Operation @ 32 MHz • 8 MHz Internal Oscillator with 4x PLL Option and Multiple Divide Options • 17-Bit x 17-Bit Single-Cycle Hardware Multiplier • 32-Bit by 16-Bit Hardware Divider • 16 x 16-Bit Working Register Array • C Compiler Optimized Instruction Set Architecture: - 76 base instructions - Flexible addressing modes • Two Address Generation Units for Separate Read and Write Addressing of Data Memory Special Microcontroller Features: • Operating Voltage Range of 2.0V to 3.6V • Flash Program Memory: - 1000 erase/write cycles - 20-year data retention minimum • Self-Reprogrammable under Software Control • Selectable Power Management modes: - Sleep, Idle and Alternate Clock modes • Fail-Safe Clock Monitor Operation: - Detects clock failure and switches to on-chip, low-power RC oscillator • On-Chip 2.5V Regulator • JTAG Boundary Scan and Programming Support • Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Flexible Watchdog Timer (WDT) with On-Chip, Low-Power RC Oscillator for Reliable Operation • In-Circuit Serial Programming™ (ICSP™) and In-Circuit Emulation (ICE) via 2 Pins Analog Features: • 10-Bit, Up to 16-Channel Analog-to-Digital Converter - 500 ksps conversion rate - Conversion available during Sleep and Idle • Dual Analog Comparators with Programmable Input/Output Configuration Peripheral Features: • Two 3-Wire/4-Wire SPI modules, Supporting 4 Frame modes with 8-Level FIFO Buffer • Two I2C™ modules Support Multi-Master/Slave mode and 7-Bit/10-Bit Addressing • Two UART modules: - Supports RS-232, RS-485 and LIN 1.2 - On-chip hardware encoder/decoder for IrDA® - Auto-wake-up on Start bit - Auto-Baud Detect - 4-level FIFO buffer • Parallel Master Slave Port (PMP/PSP): - Supports 8-bit or 16-bit data - Supports 16 address lines • Hardware Real-Time Clock/Calendar (RTCC): - Provides clock, calendar and alarm functions • Programmable Cyclic Redundancy Check (CRC) - User-programmable polynomial - 8/16-level FIFO buffer • Five 16-Bit Timers/Counters with Programmable Prescaler • Five 16-Bit Capture Inputs • Five 16-Bit Compare/PWM Outputs • High-Current Sink/Source (18 mA/18 mA) on All I/O Pins • Configurable, Open-Drain Output on Digital I/O Pins • Up to 5 External Interrupt Sources • 5.5V Tolerant Input (digital pins only)
