4-megabit 2.5-volt or 2.7-volt DataFlash® AT45DB041B For New Designs Use AT45DB041D When the device is shipped from Atmel, the most significant page of the memory array may not be erased. In other words, the contents of the last page may not be filled with FFH. 2. Pin Configurations and Packages Table 2-1. Pin Configurations 1. Description The AT45DB041B is an SPI compatible serial interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. Its 4,325,376 bits of memory are organized as 2048 pages of 264 bytes each. In addition to the main memory, the AT45DB041B also contains two SRAM data buffers of 264 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed, as well as reading or writing a continuous data stream. EEPROM emulation (bit or byte alterability) is easily handled with a self-contained three step Read-ModifyWrite operation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash uses a SPI serial interface to sequentially access its data. DataFlash supports SPI mode 0 and mode 3. The simple serial interface facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size and active pin count. The device is optimized for use in many commercial and industrial applications where high density, low pin count, low voltage, and low power are essential. The device operates at clock frequencies up to 20 MHz with a typical active read current consumption of 4 mA. To allow for simple in-system reprogrammability, the AT45DB041B does not require high input voltages for programming. The device operates from a single power supply, 2.5V to 3.6V or 2.7V to 3.6V, for both the program and read operations. The AT45DB041B is enabled through the chip select pin (CS) and accessed via a threewire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK). All programming cycles are self-timed, and no separate erase cycle is required before programming Features • Single 2.5V - 3.6V or 2.7V - 3.6V Supply • Serial Peripheral Interface (SPI) Compatible • 20 MHz Max Clock Frequency • Page Program Operation – Single Cycle Reprogram (Erase and Program) – 2048 Pages (264 Bytes/Page) Main Memory • Supports Page and Block Erase Operations • Two 264-byte SRAM Data Buffers – Allows Receiving of Data Device Operation The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Tables 1 through 4. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the CS pin is low, toggling the S CK pin controls the loading of the opcode and the desired buffer or main memory address location through the SI (serial input) pin. All instructions, addresses and data are transferred with the most significant bit (M SB) first. Buffer addressing is referenced in the datasheet using the terminology BF A 8 - BF A 0 to denote the nine address bits required to designate a byte address within a buffer. Main memory addressing is referenced using the terminology PA 10 - P A 0 and BA 8 - BA 0 where PA 1 0 - PA 0 denotes the 11 address bits required to designate a page address and BA 8 - BA 0 denotes the nine address bits required to designate a byte address within the page. Buffer Read Data can be read from either one of the two buffers, using different opcodes to specify which buffer to read from. An opcode of 54H or D4H is used to read data from buffer 1, and an opcode of 56H or D6H is used to read data from buffer 2. To perform a Buffer Read, the eight bits of the opcode must be followed by 15 don’t care bits, nine address bits, and eight don’t care bits. Since the buffer size is 264 bytes, nine address bits (BFA8 - BFA0) are required to specify the first byte of data to be read from the buffer. The CS pin must remain low during the loading of the opcode, the address bits, the don’t care bits, and the reading of data. When the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin. Status Register Read The status register can be used to determine the device’s Ready/Busy status, the result of a Main Memory Page to Buffer Compare operation, or the device density. To read the status register, an opcode of 57H or D7H must be loaded into the device. After the last bit of the opcode is shifted in, the eight bits of the status register, starting with the MSB (bit 7), will be shifted out on the SO pin during the next eight clock cycles. The five most significant bits of the status register will contain device information, while the remaining three least-significant bits are reserved for future use and will have undefined values. After bit 0 of the status register has been shifted out, the sequence will repeat itself (as long as CS remains low and SCK is being toggled) starting again with bit 7. The data in the status register is constantly updated, so each repeating sequence will output new data.
