visual studio视频教程知乎
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关 键 词：studio视频教程知乎,visual
行 业：电子 电子产品设计
发布时间：2022-11-24
ATtiny88 Automotive 8-bit AVR Microcontroller with 8K Bytes In-System Programmable Flash DATASHEET Features High performance, low power AVR 8-Bit microcontroller Advanced RISC architecture 123 powerful instructions most single clock cycle e...
minimum pulse length is given in Table 22-3 on page 209. Shorter pulses are not guaranteed togenerate a reset.The various special features of Port C are elaborated in “Alternate Functions of Port C” on page72.1.1.8Port D (PD7:0)Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit).
ThePD[7:4] output buffers have symmetrical drive characteristics with both sink and source capabil-ities, while the PD[3:0] output buffers have high sink capabilities. As inputs, Port D pins that areexternally pulled low will source current if the pull-up resistors are activated. The Port D pins aretri-stated when a reset condition becomes active, even if the clock is not running.The various special features of Port D are elaborated in “Alternate Functions of Port D” on page75.
1.1Pin Descriptions1.1.1VCCDigital supply voltage.1.1.2AVCCAVCC is the supply voltage pin for the A/D converter and a selection of I/O pins. This pin shouldbe externally connected to VCC even if the ADC is not used. If the ADC is used, it is recom-mended this pin is connected to VCC through a low-pass filter, as described in “Analog NoiseCanceling Techniques” on page 172.The following pins receive their supply voltage from AVCC: PC7, PC[5:0] and (in 32-lead pack-ages) PA[1:0].
PC6 is used as an I/O pin. Note that the electrical char-acteristics of PC6 differ from those of the other pins of Port C.If the RSTDISBL Fuse is unprogrammed, PC6 is used as a reset input. A low level on this pin forlonger than the minimum pulse width will generate a reset, even if the clock is not running. The
The ATtiny48/88 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISCarchitecture. By executing powerful instructions in a single clock cycle, the ATtiny48/88 achievesthroughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con-sumption versus processing speed.
