AT45DSP081-SU 车载主控
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行 业：电子 电子有源器件 **集成电路
发布时间：2022-05-29
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SSD102
Smart HD Display Controller
Preliminary Data Sheet Version 0.1
Security Level: Confidential A - 10 - 2/27/2018
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
MECHANICAL DIMENSIONS
E
E1
Symbol
Millimeter Inch
Min. Nom. Max. Min. Nom. Max.
A - - 1.6 - - 0.063
A1 0.05 - 0.15 0.002 - 0.006
A2 1.35 1.4 1.45 0.053 0.055 0.057
D 15.8 16 16.2 0.622 0.630 0.638
D1 13.8 14 14.2 0.543 0.551 0.559
E 15.8 16 16.2 0.622 0.630 0.638
E1 13.8 14 14.2 0.543 0.551 0.559
b 0.17 0.2 0.27 0.007 0.008 0.011
e 0.42 0.5 0.58 0.017 0.020 0.023
Sigmastar Confidential for
芯智国际有限公司
Internal Use Only
SSD102
Smart HD Display Controller
Preliminary Data Sheet Version 0.1
Security Level: Confidential A - 11 - 2/27/2018
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Symbol Min Max Units
3.3V Supply Voltages V VDD_33 3.63 V
1.2V Supply Voltages V VDD_12 1.32 V
Input Voltage (5V tolerant inputs) V IN5Vtol 5.0 V
Input Voltage (non 5V tolerant inputs) V IN V DD_33 V
Ambient Operating Temperature
T A -40 85
°C
Storage Temperature T STG -40 125 °C
Junction Temperature T J 125 °C
Note: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only and does not imply functional operation of the device. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Sigmastar Confidential for
芯智国际有限公司
Internal Use Only
SSD102
Smart HD Display Controller
Preliminary Data Sheet Version 0.1
Security Level: Confidential A - 12 - 2/27/2018
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
ORDERING GUIDE
Part Number Temperature Range Package Description Package Option
SSD102 -40°C to +85°C LQFP 100-pin
MARKING INFORMATION
SSD102
DISCLAIMER
SIGMASTAR TECHNOLOGY RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE
TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. NO
RESPONSIBILITY IS ASSUMED BY SIGMASTAR TECHNOLOGY ARISING OUT OF THE APPLICATION
OR USER OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY
LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
Electrostatic charges accumulate on both test equipment and human body and can discharge without
detection. SSD102 comes with ESD protection circuitry; however, the device may be permanently
damaged when subjected to high energy discharges. The device should be handled with proper ESD
内存（RAM） 128MB DDRII
闪存（FLASH Memory） 大支持8GB/Up to 8G
外部存储（External Memory） SD(SDHC)
操作系统（OS） Wince6.0
显示（Display） 800*480Pixels
音频（Audio Format） mp3/wma
视频（Video Format） mpeg.rmvb.rav.wmv.asf.avi.3gp.mp4.dat.mov
图片（Picture Format） ipg.png.gif.bmp
视频输出（Video Output） 数字RGB
声音输出（Audio Output） 四声道
视频输入（Video Iutput） CVBS.Y/C.YUV
声音输入（Audio Iutput） 双声道立体声/Dual track stereo speaker system
收音机（Radio） FM/AM.RDS
蓝牙（Bluetooth） 内置蓝牙免提，蓝牙音乐，电话本
数字电视（Digital TV） CMMB.ISDB-T
操作界面（UI） 多套操作界面可选，也可定制
手机互联（Phone Link） 支持手机三星.HTC.LG.SONY系列等等主流手机
DVD格式（DVD Format
Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index Name Bits Description
VDS_MTHD 6 Input data double sample Method.
0: Using average.
1: Using advance GT filter.
IVDS 5 Input VSYNC Delay Select.
0: Delay 1/4 input HSYNC (recommended).
1: No delay.
HES 4 Input HSYNC reference Edge Select.
0: From HSYNC leading edge, default value.
1: From HSYNC tailing edge.
VES 3 Input VSYNC reference Edge Select.
0: From VSYNC leading edge, default value.
1: From VSYNC tailing edge.
ESLS 2 Early Sample Line Select.
0: 8 lines.
1: 16 lines.
VWRP 1 Input image Vertical Wrap.
0: Disable.
1: Enable.
HWRP 0 Input image Horizontal Wrap.
0: Disable.
1: Enable.
04h ISCTRL 7:0 Default : 0x10 Access : R/W
DDE 7 Direct DE mode for CCIR input.
0: Disable direct DE.
1: Enable direct DE.
DEGR[2:0] 6:4 DE or HSYNC post Glitch removal Range.
HSFL 3 Input HSYNC Filter.
0: Filter off.
1: Filter on.
ISSM 2 Input Sync Sample Mode.
0: Normal.
1: Glitch-removal.
MVD_SEL 1:0 MVD mode Select
0: CVBS.
1: S-Video.
2: YCbCr.
3: RGB.
05h SPRVST_L 7:0 Default : 0x10 Access : R/W, DB
Sigmastar Confidential for
芯智国际有限公司
Internal Use Only
Security Level: Confidential A
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index Name Bits Description
SPRVST[7:0] 7:0 Image vertical sample start point, count by input HSYNC (lower 8
bits).
06h SPRVST_H 7:0 Default : 0x00 Access : R/W, DB
- 7:3 Reserved.
SPRVST[10:8] 2:0 Image vertical sample start point, count by input HSYNC (higher 3
bits).
07h SPRHST_L 7:0 Default : 0x01 Access : R/W, DB
SPRHST[7:0] 7:0 Image horizontal sample start point, count by input dot clock
(lower 8 bits).
08h SPRHST_H 7:0 Default : 0x00 Access : R/W, DB
- 7:4 Reserved.
SPRHST[11:8] 3:0 Image horizontal sample start point, count by input dot clock
(higher 4 bits).
09h SPRVDC_L 7:0 Default : 0x10 Access : R/W, DB
SPRVDC[7:0] 7:0 Image vertical resolution (vertical display enable area count by
line; lower 8 bits).
0Ah SPRVDC_H 7:0 Default: 0x00 Access : R/W
- 7:3 Reserved.
SPRVDC[10:8] 2:0 Image vertical resolution (vertical display enable area count by
line; higher 3 bits).
0Bh SPRHDC_L 7:0 Default : 0x10 Access : R/W
SPRHDC[7:0] 7:0 Image horizontal resolution (horizontal display enable area count
by pixel; lower 8 bits).
0Ch SPRHDC_L 7:0 Default : 0x00 Access : R/W
- 7:3 Reserved.
SPRHDC[11:8] 3:0 Image horizontal resolution (horizontal display enable area count
by pixel; higher 4 bits).
0Dh LYL 7:0 Default : 0x00 Access : R/W
- 7:4 Reserved.
LYL[3:0] 3:0 Lock Y Line.
0Eh INTLX 7:0 Default : 0x00 Access : -
ITU_EXT_FIELD 7 Using External FIELD for ITU interface.
Security Level: Confidential A - 12 - 2/27/2018
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
ORDERING GUIDE
Part Number Temperature Range Package Description Package Option
SSD102 -40°C to +85°C LQFP 100-pin
MARKING INFORMATION
SSD102
DISCLAIMER
SIGMASTAR TECHNOLOGY RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE
TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. NO
RESPONSIBILITY IS ASSUMED BY SIGMASTAR TECHNOLOGY ARISING OUT OF THE APPLICATION
OR USER OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY
LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
Electrostatic charges accumulate on both test equipment and human body and can discharge without
detection. SSD102 comes with ESD protection circuitry; however, the device may be permanently
damaged when subjected to high energy discharges. The device should be handled with proper ESD
precautions to prevent malfunction and performance degradation.
Sigmastar Confidential for
芯智国际有限公司
Internal Use Only
Security Level: Confidential A
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
REGISTER DESCRIPTION
General Control Register
General Control Register
Index Name Bits Description
00h
REGBK 7:0 Default : 0x00 Access : R/W
XTAL_OK (RO) 7 Crystal ready.
MCU_SEL (RO) 6 0: Embedded MCU.
1: External serial bus interface.
- 5:4 Reserved.
AINC 3 Serial bus address auto Increase.
0: Enable.
1: Disable.
- 2 Reserved.
REGBK[1:0] 1:0 Register Bank Select.
00: Register of scaler.
01: Register of ADC/ACE/MCU.
10: Register of Video Decoder Front End (VFE).
11: Register of Video Decoder 2D Comb Filter (VCF).
REGBK[2:0] 2:0 Register Bank Select.
000: Register of scaler.
001: Register of ADC/ACE/MCU.
010: Register of Video Decoder Front End (VFE).
011: Register of Video Decoder 2D Comb Filter (VCF)
01h ~
FFh
- 7:0 Default : - Access : -
- 7:0 Reserved.
Scaler Register (Bank = 00, Registers 01h ~ 9Fh)
Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index Name Bits Description
01h
DBFC 7:0 Default : 0x80 Access : R/W
- 7:3 Reserved.
DBL[1:0] 2:1 Double Buffer Load.
00: Keep old register value.
01: Load new data (auto reset to 00 when load finish).
10: Automatically load data at VSYNC blanking.
11: Reserved.
Sigmastar Confidential for
芯智国际有限公司
Internal Use Only
Security Level: Confidential A
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index Name Bits Description
DB_EN 0 Double Buffer Enable.
0: Disable.
1: Enable.
02h ISELECT 7:0 Default : 0x00 Access : R/W
NIS 7 No Input Source.
0: Input source active.
1: Input source inactive, output is free-run.
STYPE[1:0] 6:5 Input Sync Type.
00: Auto detected.
01: Input is separated HSYNC and VSYNC.
10: Input is Composite sync.
11: Input is sync-on-green (SOG).
COMP 4 CSYNC/SOG select (only useful when STYPE = 00).
0: CSYNC.
1: SOG.
ICS 3 Input Color Space.
0: RGB.
1: YCbCr.
IHSU 2 Input Sync Usage.
When EXTVD=0:
0: Use HSYNC to perform mode detection, HSOUT from ADC to
sample pixel.
1: Use HSYNC only.
When EXTVD=1:
0: Normal.
1: Output black at blanking.
BYPASSMD 1 By-Pass Mode for interlace-input-interlace-output.
EXTVD 0 0: Select analog input (CVBS/S-Video/RGB/YCbCr).
1: Select digital input (CCIR656).
03h IPCTRL2 7:0 Default : 0x18 Access : R/W
VDS_EN 7 Input data double sample
In CCIR input mode,
0: for horizontal output resolution less than 720 pixels.
1: for horizontal output resolution more than 720 pixels.
In analog input mode,
0: half sample of input data.
1: original sample of input data.
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